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october 2009 doc id 15632 rev 1 1/29 1 VNN7NV04P-E, vns7nv04p-e omnifet ii fully autoprotected power mosfet features linear current limitation thermal shutdown short circuit protection integrated clamp low current drawn from input pin diagnostic feedback through input pin esd protection direct access to the gate of the power mosfet (analog driving) compatible with standa rd power mosfet in compliance with the 2002/95/ec european directive description the VNN7NV04P-E, vns7nv04p-e, are monolithic devices designed in stmicroelectronics vipower? m0-3 technology, intended for replacement of standard power mosfets from dc up to 50 khz applications. built in thermal shutdown , linear current limitation and overvoltage clamp protect the chip in harsh environments. fault feedback can be detected by monitoring the voltage at the input pin. type r ds(on) i lim v clamp VNN7NV04P-E vns7nv04p-e 60 m 6a 40v table 1. device summary package order codes tube tape and reel sot-223 - vnn7nv04ptr-e so-8 vns7nv04p-e vns7nv04ptr-e sot-223 so-8 1 2 2 3 www.st.com
contents VNN7NV04P-E, vns7nv04p-e 2/29 doc id 15632 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 so-8 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 sot-223 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . 17 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 so-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 sot-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 sot-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 so-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 sot-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 so-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VNN7NV04P-E, vns7nv04p-e list of tables doc id 15632 rev 1 3/29 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. so-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. sot-223 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. sot-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. so-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of figures VNN7NV04P-E, vns7nv04p-e 4/29 doc id 15632 rev 1 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 12 figure 13. source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 14. static drain source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15. turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16. turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 17. transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 18. static drain-source on resistance vs id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 19. input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 20. turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 21. turn-off drain source voltage slope (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 22. capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 23. output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 24. normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 25. switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 26. switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 27. normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 28. normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 29. step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 30. so-8 maximum turn-off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 31. so-8 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 32. sot-223 maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . 17 figure 33. sot-223 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 34. so-8 pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 35. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 18 figure 36. so-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 37. thermal fitting model of an omnifet ii in so-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 38. sot-223 pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 39. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20 figure 40. sot-223 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . 21 figure 41. thermal fitting model of an omnifet ii in sot-223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 42. sot-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 43. so-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 44. sot-223 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 45. so-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 46. so-8 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7
VNN7NV04P-E, vns7nv04p-e block diagram and pin description doc id 15632 rev 1 5/29 1 block diagram and pin description figure 1. block diagram figure 2. configurati on diagram (top view) 1. for the pins configuration relat ed to sot-223 see outlines at page 1. overvoltage gate linear drain source clamp 1 2 3 current limiter control over temperature input fc01000 so-8 package (1) drain drain drain drain input source source source 1 4 5 8
electrical specifications VNN7NV04P-E, vns7nv04p-e 6/29 doc id 15632 rev 1 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings drain input source i d i in v in v ds r in table 2. absolute maximum ratings symbol parameter value unit sot-223 so-8 v ds drain-source voltage (v in =0 v) internally clamped v v in input voltage internally clamped v i in input current +/-20 ma r in min minimum input series impedance 150 i d drain current internally limited a i r reverse dc output current -10.5 a v esd1 electrostatic discharge (r=1.5 k , c=100 pf) 4000 v v esd2 electrostatic discharge on output pin only (r=330 , c=150 pf) 16500 v p tot total dissipation at t c =25 c 7 4.6 w e max maximum switching energy (l=0.7 mh; r l =0 ; v bat =13.5 v; t jstart =150 oc; i l =9 a) 40 mj e max maximum switching energy (l=0.6 mh; r l =0 ; v bat =13.5 v; t jstart =150 oc; i l =9 a) 37 mj t j operating junction temperature internally limited c t c case operating temperature internally limited c t stg storage temperature -55 to 150 c
VNN7NV04P-E, vns7nv04p-e electrical specifications doc id 15632 rev 1 7/29 2.2 thermal data 2.3 electrical characteristics -40 c < t j < 150 c, unless otherwise specified. table 3. thermal data symbol parameter value unit sot-223 so-8 r thj-case thermal resistance junction-case max 18 c/w r thj-lead thermal resistance junction-lead max 27 c/w r thj-amb thermal resistance j unction-ambient max 96 (1) 1. when mounted on a standard single-sided fr4 board with 0.5 mm 2 of cu (at least 35 m thick) connected to all drain pins . 90 (1) c/w table 4. electrical characteristics symbol parameter test conditions min typ max unit off v clamp drain-source clamp voltage v in =0 v; i d =3.5 a 40 45 55 v v clth drain-source clamp threshold voltage v in =0 v; i d =2 ma 36 v v inth input threshold voltage v ds =v in ; i d =1 ma 0.5 2.5 v i iss supply current from input pin v ds =0 v; v in =5 v 100 150 a v incl input-source clamp voltage i in =1 ma i in =-1 ma 6 -1.0 6.8 8 -0.3 v i dss zero input voltage drain current (v in =0 v) v ds =13 v; v in =0 v; t j =25 c v ds =25 v; v in =0 v 30 75 a on r ds(on) static drain-source on resistance v in =5 v; i d =3.5 a; t j =25 c v in =5 v; i d =3.5 a 60 120 m dynamic (t j =25 c, unless otherwise specified) g fs (1) forward transconductance v dd =13 v; i d =3.5 a 9 s c oss output capacitance v ds =13v; f=1mhz; v in =0 v 220 pf switching (t j =25 c, unless otherwise specified)
electrical specifications VNN7NV04P-E, vns7nv04p-e 8/29 doc id 15632 rev 1 t d(on) turn-on delay time v dd =15 v; i d =3.5 a v gen =5 v; r gen =r in min =150 (see figure figure 4 ) 100 300 100 ns t r rise time 470 1500 470 ns t d(off) turn-off delay time 500 1500 500 ns t f fall time 350 1000 350 ns t d(on) turn-on delay time v dd =15 v; i d =3.5 a v gen =5 v; r gen =2.2 k (see figure figure 4 ) 0.75 2.3 0.75 s t r rise time 4.6 14.0 4.6 s t d(off) turn-off delay time 5.4 16.0 5.4 s t f fall time 3.6 11.0 3.6 s (di/dt) on turn-on current slope v dd =15 v; i d =3.5 a v gen =5 v; r gen =r in min =150 6.5 6.5 a/s q i total input charge v dd =12 v; i d =3.5 a; v in =5 v i gen =2.13 ma (see figure figure 7 ) 18 nc source drain diode (t j =25 c, unless otherwise specified) v sd (1) forward on voltage i sd =3.5 a; v in =0 v 0.8 v t rr reverse recovery time i sd =3.5 a; di/dt=20 a/s v dd =30 v; l=200 h (see test circuit, figure figure 5 ) 220 ns q rr reverse recovery charge 0.28 c i rrm reverse recovery current 2.5 a protections (-40 c < t j < 150 c, unless otherwise specified) i lim drain current limit v in =5 v; v ds =13 v 6 9 12 a t dlim step response current limit v in =5 v; v ds =13 v 4.0 s t jsh overtemperature shutdown 150 175 200 c t jrs overtemperature reset 135 c i gf fault sink current v in =5 v; v ds =13 v; t j =t jsh 15 ma e as single pulse avalanche energy starting t j =25 c; v dd =24 v v in =5 v r gen =r in min =150 ; l=24 mh (see figures figure 6 & figure 8 ) 200 mj 1. pulsed: pulse duration = 300 s, duty cycle 1.5 % table 4. electrical characteristics (continued) symbol parameter test conditions min typ max unit
VNN7NV04P-E, vns7nv04p-e protection features doc id 15632 rev 1 9/29 3 protection features during normal operation, the input pin is electrically connected to the gate of the internal power mosfet through a low impedance path. the device then behaves like a standard power mosfet and can be used as a switch from dc up to 50 khz. the only difference from the user?s standpoint is that a small dc current i iss (typ. 100a) flows into the input pin in order to supply the internal circuitry. the device integrates: overvoltage clamp protection: internally set at 45 v, along with the rugged avalanche characteristics of the power mosfet stage give this device unrivalled ruggedness and energy handling capability. th is feature is mainly import ant when driving inductive loads. linear current limiter circuit: limits the drain current i d to i lim whatever the input pin voltages. when the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of t he heatsink. both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold t jsh . overtemperature and short circuit protecti on: these are based on sensing the chip temperature and are not dependent on the input voltage. the location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. overtemperature cutout occurs in the range 150 to 190 c, a typical value being 170 c. the device is automatically restarted when the chip temperature falls of about 15 c below shutdown temperature. status feedback: in the case of an overtemperature fault condition (t j > t jsh ), the device tries to sink a diagnostic current i gf through the input pin in order to indicate fault condition. if driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown . if the drive impedance is high enough so that the input pin driver is not able to supply the current i gf , the input pin falls to 0 v. this however not affects the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current i iss . additional features of this device are esd protection according to the human body model and the ability to be driven from a ttl logic circuit.
protection features VNN7NV04P-E, vns7nv04p-e 10/29 doc id 15632 rev 1 figure 4. switching time test circuit for resistive load figure 5. test circuit fo r diode recovery times t i d 90% 10% t v gen t d(on) t d(off) t f t r l=100uh a b 8.5 v dd r gen fast diode omnifet a d i s 150 b omnifet d s i v gen
VNN7NV04P-E, vns7nv04p-e protection features doc id 15632 rev 1 11/29 figure 6. unclamped inductive load test circuits figure 7. input charge test circuit figure 8. unclamped inductive waveforms r gen p w v in v in
protection features VNN7NV04P-E, vns7nv04p-e 12/29 doc id 15632 rev 1 3.1 electrical char acteristics curves figure 9. derating curve figure 10. transconductance figure 11. static drain-source on resistance vs input voltage (part 1/2) figure 12. static drain-source on resistance vs input voltage (part 2/2) figure 13. source-drain diode forward characteristics figure 14. static drain source on resistance 012345678 id(a) 0 2 4 6 8 10 12 14 16 18 20 gfs (s) vds=13v tj=25oc tj=150oc tj=-40oc 33.544.555.566.57 vin(v) 0 10 20 30 40 50 60 70 80 90 100 110 120 rds(on) (mohm) id=3.5a tj=150oc tj= - 40oc tj=25oc 33.5 44.5 55.5 66.5 vin(v) 0 20 40 60 80 100 120 140 rds(on) (mohm) id=6a id=1a id=6a id=1a id=6a id=1a tj=25oc tj=150oc tj=-40oc 0 2 4 6 8 101214 id(a) 500 550 600 650 700 750 800 850 900 950 1000 vsd (mv) vin=0v 0123456 id(a) 0 25 50 75 100 125 150 rds(on) (mohms) tj=25oc tj=150oc tj=-40oc vin=5v
VNN7NV04P-E, vns7nv04p-e protection features doc id 15632 rev 1 13/29 figure 15. turn-on current slope (part 1/2) figure 16. turn-on current slope (part 2/2) figure 17. transfer characteristics figure 18. static drain-source on resistance vs id figure 19. input voltage vs input charge figure 20. turn-off drain source voltage slope (part 1/2) 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 di/dt(a/us) vin=3.5v vdd=15v id=3.5a 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0 1 2 3 4 5 6 7 8 di/dt(a/us) vin=5v vdd=15v id=3.5a 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 vin ( v ) 0 1 2 3 4 5 6 7 8 9 10 idon(a) vds=13.5v tj=150oc tj=25oc tj=-40oc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 id(a) 0 20 40 60 80 100 120 140 rds(on) (mohm) tj=25oc tj=150oc tj=-40oc vin=5v vin=3.5v vin=5v vin=5v vin=3.5v vin=3.5v 0 5 10 15 20 25 qg(nc) 0 1 2 3 4 5 6 7 8 vin(v) vds=12v id=3.5a 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0 50 100 150 200 250 300 dv/dt(v/us) vin=5v vdd=15v id=3.5a
protection features VNN7NV04P-E, vns7nv04p-e 14/29 doc id 15632 rev 1 figure 21. turn-off drain source voltage slope (part 2/2) figure 22. capacitance variations figure 23. output characteristics figure 24. normalized on resistance vs temperature v figure 25. switching time resistive load (part 1/2) figure 26. switching time resistive load (part 2/2) 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0 50 100 150 200 250 300 dv/dt(v/us) vin=3.5v vdd=15v id=3.5a 0 5 10 15 20 25 30 35 vds(v) 100 200 300 400 500 600 c(pf) f=1mhz vin=0v 0 1 2 3 4 5 6 7 8 9 10 11 12 13 vds(v) 0 1 2 3 4 5 6 7 8 9 10 11 12 id(a) vin=2.5v vin=4v vin=4.5v vin=3v vin=2v vin=5v -50 -25 0 25 50 75 100 125 150 175 t(oc) 0.5 0.75 1 1.25 1.5 1.75 2 2.25 rds(on) vin=5v id=3.5a 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 rg(ohm) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 t(us) td(on) tf td(off) tr vdd=15v id=3.5a vin=5v 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 vin(v) 0 200 400 600 800 1000 1200 1400 1600 t(ns) tf tr td(on) td(off) vdd=15v id=3.5a rg=150ohm
VNN7NV04P-E, vns7nv04p-e protection features doc id 15632 rev 1 15/29 figure 27. normalized input threshold voltage vs temperature figure 28. normalized current limit vs junction temperature figure 29. step response current limit -50 -25 0 25 50 75 100 125 150 175 t(oc) 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 vin(th) vds=vin id=1ma -50 -25 0 25 50 75 100 125 150 175 tj (oc) 5 6 7 8 9 10 11 12 13 14 15 ilim (a) vds=13v vin=5v 5 101520253035 vdd(v) 3.5 4 4.5 5 5.5 6 6.5 7 tdlim(us) vin=5v rg=150ohm
protection features VNN7NV04P-E, vns7nv04p-e 16/29 doc id 15632 rev 1 3.2 so-8 maximum de magnetization energy figure 30. so-8 maximum turn-off current versus load inductance legend a = single pulse at t jstart =150 c b = repetitive pulse at t jstart =100 c c = repetitive pulse at t jstart =125 c conditions: v cc =13.5 v values are generated with r l =0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. figure 31. so-8 demagnetization 1 10 100 0.1 1 10 100 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
VNN7NV04P-E, vns7nv04p-e protection features doc id 15632 rev 1 17/29 3.3 sot-223 maximum de magnetization energy figure 32. sot-223 maxi mum turn-off current ve rsus load inductance legend a = single pulse at t jstart =150 c b = repetitive pulse at t jstart =100 c c = repetitive pulse at t jstart =125 c conditions: v cc =13.5 v values are generated with r l =0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. figure 33. sot-223 demagnetization 1 10 100 0.01 0.1 1 10 l(mh) i lmax (a) v in , i l t demagnetization demagnetization demagnetization
package and pcb thermal da ta VNN7NV04P-E, vns7nv04p-e 18/29 doc id 15632 rev 1 4 package and pcb thermal data 4.1 so-8 thermal data figure 34. so-8 pc board note: layout condition of r th and z th measurements (pcb fr4 area=58 mm x 58 mm, pcb thickness=2 mm, cu thickness=35 m, copper areas: 0.14 cm 2 , 0.8 cm 2 , 2 cm 2 ). figure 35. r thj-amb vs pcb copper area in open box free air condition 70 75 80 85 90 95 100 105 110 00.511.522.5 pcb cu heatsink area (cm^2) rt hj _am b ( oc/w) so-8 at 2 pins connected to tab
VNN7NV04P-E, vns7nv04p-e package and pcb thermal data doc id 15632 rev 1 19/29 figure 36. so-8 thermal impedance junction ambient single pulse figure 37. thermal fitting model of an omnifet ii in so-8 equation 1 pulse calculation formula where table 5. so-8 thermal parameter area/island (cm 2 ) footprint 2 r1 (c/w) 0.2 r2 (c/w) 0.9 r3 (c/w) 3.5 r4 (c/w) 21 r5 (c/w) 16 r6 (c/w) 58 28 c1 (w.s/c) 3.00e-04 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj z th r th z thtp 1 ? () + ? = t p t ? =
package and pcb thermal da ta VNN7NV04P-E, vns7nv04p-e 20/29 doc id 15632 rev 1 4.2 sot-223 thermal data figure 38. sot-223 pc board note: layout condition of r th and z th measurements (pcb fr4 area=58 mm x 58 mm, pcb thickness=2 mm, cu thickness=35 m, copper areas: 0.11 cm 2 , 1 cm 2 , 2 cm 2 ). figure 39. r thj-amb vs pcb copper area in open box free air condition c2 (w.s/c) 9.00e-04 c3 (w.s/c) 7.50e-03 c4 (w.s/c) 0.045 c5 (w.s/c) 0.35 c6 (w.s/c) 1.05 2 table 5. so-8 thermal parameter (continued) area/island (cm 2 ) footprint 2 60 70 80 90 100 110 120 130 140 0 0.5 1 1.5 2 2.5 cu area (cm^2) rth j-amb (c/w)
VNN7NV04P-E, vns7nv04p-e package and pcb thermal data doc id 15632 rev 1 21/29 figure 40. sot-223 thermal impedance junction ambient single pulse figure 41. thermal fitting model of an omnifet ii in sot-223 equation 2 pulse calculation formula where table 6. sot-223 thermal parameter area/island (cm 2 ) footprint 2 r1 (c/w) 0.2 r2 (c/w) 1.1 r3 (c/w) 4.5 r4 (c/w) 24 r5 (c/w) 0.1 r6 (c/w) 100 45 c1 (w.s/c) 3.00e-04 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj z th r th z thtp 1 ? () + ? = t p t ? =
package and pcb thermal da ta VNN7NV04P-E, vns7nv04p-e 22/29 doc id 15632 rev 1 c2 (w.s/c) 9.00e-04 c3 (w.s/c) 3.00e-02 c4 (w.s/c) 0.16 c5 (w.s/c) 1000 c6 (w.s/c) 0.5 2 table 6. sot-223 thermal parameter (continued) area/island (cm 2 ) footprint 2
VNN7NV04P-E, vns7nv04p-e package and packing information doc id 15632 rev 1 23/29 5 package and packing information in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack? is an st trademark. 5.1 sot-223 mechanical data figure 42. sot-223 package dimensions table 7. sot-223 mechanical data symbol millimeters min. typ. max. a 1.8 b0.60.70.85 b1 2.9 3 3.15 c 0.24 0.26 0.35 d6.36.56.7 e2.3 e1 4.6 e3.33.53.7 h6.777.3 v 10 (max) a1 0.02 0.1 0046067
package and packing information VNN7NV04P-E, vns7nv04p-e 24/29 doc id 15632 rev 1 5.2 so-8 mechanical data table 8. so-8 mechanical data symbol millimeters min typ max a 1.75 a1 0.1 0.25 a2 1.65 a3 0.65 0.85 b 0.35 0.48 a 1.75 a1 0.10 0.25 a2 1.25 b 0.28 0.48 c 0.17 0.23 d (1) 1. dimension ?d? does not include mold fl ash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side). 4.80 4.90 5.00 e 5.80 6.00 6.20 e1 (2) 2. dimension ?e1? does not include interlead flash or pr otrusions. interlead flash or protrusions shall not exceed 0.25 mm per side. 3.80 3.90 4.00 e 1.27 h 0.25 0.50 l 0.40 1.27 l1 1.04 k 0 8 ccc 0.10
VNN7NV04P-E, vns7nv04p-e package and packing information doc id 15632 rev 1 25/29 figure 43. so-8 package dimensions 0016023 d
package and packing information VNN7NV04P-E, vns7nv04p-e 26/29 doc id 15632 rev 1 5.3 sot-223 packing information figure 44. sot-223 tape and reel shipment (suffix ?tr?) reel dimensions base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
VNN7NV04P-E, vns7nv04p-e package and packing information doc id 15632 rev 1 27/29 5.4 so-8 packing information figure 45. so-8 tube shipment (no suffix) figure 46. so-8 tape and reel shipment (suffix ?tr?) base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 c b a tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4
revision history VNN7NV04P-E, vns7nv04p-e 28/29 doc id 15632 rev 1 6 revision history table 9. document revision history date revision changes 15-oct-2009 1 initial release.
VNN7NV04P-E, vns7nv04p-e doc id 15632 rev 1 29/29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military , air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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